In order to find true utility in a modern, high-speed switching application, a gate drive circuit for a power transistor must meet several basic criteria.
The gate drive must ensure that the power transistor will not be inadvertently turned ON at any time during steady-state operation, initial power-up, or during shutdown of the gate drive. The gate drive must prevent inadvertent turn ON as a result of factors such as: electromagnetic interference present in the operating environment of the power transistor; spurious electrical noise inherent in the operation of associated circuitry; or inherent parasitic capacitances present within the power transistor. Particularly in high power applications, inadvertent turn ON of the power transistor may result in severe damage or destruction of the power transistor and the circuit in which the power transistor is utilized.
The gate drive must also be capable of achieving very rapid switching rates, on the order of a few hundred nanoseconds for some applications, in order to allow the precise timing of switching the power transistor necessary for minimizing harmonic distortion at electrical loads connected to the power transistor.
The gate drive must further provide a convenient electrical interface between the power transistor and associated control logic circuitry. Control of the gate drive is typically provided by control circuitry external to the gate drive. Such external control circuitry typically utilizes microprocessor based logic circuitry which functions with low voltage potential electrical signals. The gate drive must provide conversion of low voltage potential control signals received from the external control circuitry to high voltage potential signals required for switching the power transistor.
In attempting to satisfy the basic criteria defined above, it is well known in the art to utilize transformers for coupling the gate drive between associated control logic circuitry and the power transistor. Transformer coupling provides dielectric isolation of the gate drive-from spurious noise in control circuitry and allows control signal voltages to be stepped up or down to facilitate electrical interfacing with associated circuitry. It is also well known in the art that by providing a reverse-bias voltage across the gate-emitter junction of the power transistor during the OFF state, the resistance of the power transistor to inadvertent turn ON is greatly enhanced. It is further well known in the art that switching speed of the power transistor may be increased by incorporating energy storage devices such as capacitors into the gate drive which inject an electrical charge into the power transistor at the instant of switching in order to quickly extinguish charge carriers accumulated within the transistor.
An example of a prior gate drive circuit incorporating transformer coupling is provided by FIGS. 21-27 and associated text on pages 564 and 565 of a standard textbook entitled POWER ELECTRONICS: CONVERTERS, APPLICATIONS, DESIGN by Mohan, Undeland, and Robbins, (Wiley, New York 1989). Mohan describes a transformer-isolated gate drive having a single coupling transformer utilized to couple both control signals and bias power signals from an external control circuit to the gate drive. The circuit of Mohan et al does not, however, incorporate provisions for providing a reverse-bias voltage to ensure holding the power transistor in the OFF state. The circuit of Mohan et al also introduces significant delay at turn OFF since resistor R2 and capacitor C2, as shown in FIGS. 21-27, must discharge before turn OFF can occur.
U.S. Pat. No. 4,605,865 to Yuzurihara describes an input drive apparatus for a power transistor utilizing a two phase oscillator in conjunction with multiple transformers having air gaps to provide electrical insulation between an input side circuit means and an output side circuit means. Electromagnetic energy stored in the transformers is utilized as a source of bias voltage for the power transistor. The input drive apparatus of Yuzurihara does not provide energy storage devices downstream of the transformers for increasing switching speed of the power transistor, and further does not incorporate provisions for providing a sustained reverse-bias voltage across the power transistor during the OFF state to preclude inadvertent turn ON of the power transistor.
U.S. Pat. No. 4,694,206 to Weinberg describes a drive circuit for a power field effect transistor utilizing two switching circuits connected between the gate and source electrodes of a field effect transistor, with each of the switching circuits comprising a controlled switch and a secondary winding of a pulse transformer to provide electrical isolation between the control electronics and the power switching circuit of the field effect transistor: The drive circuit of Weinberg further provides short switching delay times and provides a negative gate-source voltage during the OFF period by periodically recharging the gate-source capacitance inherent within the field effect transistor. The drive circuit of Weinberg does not, however, provide energy storage downstream of the pulse transformers for increasing switching speed of the power transistor by injecting electrical charge to rapidly extinguish accumulated carrier charges, and further, does not incorporate means for providing a sustained reverse-bias voltage across the field effect transistor during the OFF state to preclude inadvertent turn ON of the field effect transistor.
U.S. Pat. No. 4,748,351 to Barzegar describes a power MOSFET gate driver circuit providing reduced noise susceptibility which utilizes dual drive paths to provide turn-ON and turn-OFF bias signals to the gate of the MOSFET via a pulse transformer having two serially connected secondary windings. Turn-ON pulses are coupled by a diode from the first secondary to the MOSFET gate. Turn-OFF pulses are coupled via the second secondary to a control MOSFET which is turned ON by a turn-OFF pulse and remains. ON to keep the gate of the MOSFET switch at a hold-OFF voltage for a period of time after the MOSFET is turned ON. The diode of Barzegar, however, only keeps the gate of the MOSFET high, and thus at hold-OFF voltage, until the transformer 110 of Barzegar saturates. Once the transformer reaches saturation, the hold-OFF voltage is lost. This sort of saturation and loss of the hold-OFF voltage is a serious problem in the design of practical inverters. Without a sustained hold-OFF voltage, the inverter can be inadvertently turned on as described above.
Barzegar cannot be said, therefore, to provide sustained reverse-bias voltage across the field effect transistor during the OFF-state to preclude inadvertent turn ON of the field effect transistor. Furthermore, Barzegar does not provide means for energy storage downstream of the pulse transformer for increasing switching speed of the MOSFET by injecting electrical charge to rapidly extinguish accumulated carrier charges.
U.S. Pat. No. 5,019,719 to King describes a transformer coupled gate drive circuit for power MOSFETs which produces a sharply rising gate drive signal to improve switching speed, and which provides electrical isolation through transformer coupling. The gate drive of King includes a pair of low power switching devices and a storage capacitor coupled through a transformer to a CMOS switching circuit. The storage capacitor of King is utilized to increase switching speed of the MOSFET. King does not, however, include means for providing a sustained reverse-bias voltage across the MOSFET during the OFF state to preclude inadvertent turn ON of the MOS FET.
Although each of the gate drives referenced above incorporates means for achieving one or more of the basic criteria for utility, none of them, when considered individually or in combination, represents a gate drive which meets all of the basic criteria for utility defined herein. The invention to be described hereinafter, advances the state of the art in gate drives for power transistors by providing means for satisfying all of the basic criteria for utility defined herein.